A smart card is referred to as an IC card in Japan, which is generally classified into two types: a contact smart card and a contactless smart card. There are various types of contact smart cards, which are different in frequencies of clock signals required. For example, one smart card requires 4 MHz and 8 MHz, another smart card requires 4.5 MHZ, 6.75 MHz, and 13.5 MHz, and still another smart card requires 4.608 MHz, 9.216 MHz, and 18.432 MHz. In ISO7816-3 which defines the electrical characteristics of the contact smart card, it is specified that duty cycle of the clock signal shall be between 45% and 55% of the period during stable operation. Therefore, it is necessary to generate clock signals having these frequencies and complying with ISO7816-3.
When there is a need for a frequency freq between a frequency CLK/A obtained by dividing a frequency CLK by A and a frequency CLK/(A+1) obtained by dividing the frequency CLK by (A+1), it is necessary to correct the remainder of CLK/freq. The document described below discloses a method of correcting the remainder.
Japanese Patent Laid-Open No. 2001-308697 (patent document 1 described below) discloses a frequency generation circuit capable of generating clock signals having various frequencies. The frequency generation circuit comprises divide-by-n means for dividing a clock signal having a frequency K by n, pause control signal output means for outputting a 1/K-sec pause control signal i times after or while the divide-by-n means repeats m times the process of dividing the clock signal by n, and output stop means for stopping an output of the divide-by-n means according to the pause control signal or for stopping an input of the divide-by-n means according to the pause control signal and stopping an output of the divide-by-n means by means of the input stop operation, so as to generate clock signals having a frequency of m×K(n×m+i).
Since this frequency generation circuit corrects the remainder at a time, however, the corrected portions are unevenly distributed, thereby generating an unbalanced output clock signal.
Japanese Patent laid-Open No. Hei 11-220384 (patent document 2 described below) discloses a frequency generation circuit for generating a pulse having a predetermined frequency C1 from a pulse having a reference frequency Co. The frequency generation circuit generates the pulse having the predetermined frequency C1 by equally distributing a residual (a remainder of Co/C1) between the divided pulse generated by dividing the pulse having the reference frequency Co and the pulse having the reference frequency Co to the divided pulses. More specifically, the frequency generation circuit includes: dividing means for generating a pulse having a predetermined frequency C1 by dividing a pulse having a reference frequency Co by an integer value Ko; first correction means for dividing the pulse having the predetermined frequency C1 by an integer value K1, generating a pulse having a residual frequency C2 generated by the dividing of the dividing means, and correcting the pulse generated by the dividing means; and i-th correction means for dividing a pulse having a residual frequency Ci (i is 2 or a greater integer) by an integer value Ki, generating a pulse having a residual frequency Ci+1 generated by an (i˜1) correction means, and correcting a pulse output from the (i˜1) correction means).
While this frequency generation circuit can equally distribute the remainder (the residual), it has a limit to the number of the correction means mounted thereon and thus, if in future the required predetermined frequency C1 increases in variety, a larger error is expected as to a generated predetermined frequency C1.
Moreover, no circuits employ measures to maintain the duty cycle within an allowable range and therefore they do not comply with ISO7816-3.